sany o inv e rter power hy br id modul e sip full m o lded package tent a tive igbt 600v/10a high s peed STK621-015 1. overview : this ic is a 3-phase i n verter power hybrid i c cont ainin g power element s (igbt and fr d), pre-driver , over-current protection circuit. 2. application: 3-phase inverter motor . induct i on motor . blushless-dc motor 3. features: integrates p o wer eleme n t s (igbt and frd), pre-driver , and protective circuit. ? ? ? ? ? ? protective circuit s including over-current (bus line), and pre-d r ive low volt age protection are built in. direct input of cmos level control signals wit hout an insulating circu i t (photo-co upler , etc) is possible. a single po wer supply drive is ena bled throug h the use o f boot strap circuit s for upper power supplies. (e xternally set) built-in sim u lt aneous upper/lower on preve n tion cir c uit to prevent arm shorting throug h simult aneous on input for the up per and lo wer side transistors. ( d ead time is required f o r preventing shorting due t o switching delay .) sip (the sin g le in-line p a ckage) of t he transfer f u ll mold stru cture. 4. absolute maximum ratings at ?s c=25 ?? paramete r s y m b o l rating s unit rema r k s supply volt ag e vcc 500 v + to - pin s , su rge < 60 0v colle ctor-emi tter volt age vce 600 v + to u(v , w) o r u(v , w) to -, no operating. output c u rrent io ?} 10 a + , -, u, v , w terminal c u rrent output pea k curre n t iop ?} 15 a + , -, u, v , w terminal c u rrent pw= 1 00usec pre-driver s u pply volt age vd1,2,3,4 20 v vb1 - u, vb2 - v , vb3 - w , vdd - vss * input sign al volt age vin 0 to 7 v hin1,2,3,li n 1,2,3 terminal f a ul t termin al volt age vf aul t 20 v f a ul t termin al maximum loss pd 15 w per 1 ch ann e l jun c tion tem peratu r e tj 150 ?? igbt ,frd ju nction temp erature s t orage temp eratu r e t s t g -40 to +125 ?? operating te mperature tc -20 to +100 ?? h-ic ca se te mperature mounting torque 1.0 nm a screw p a rt in the case without the instruction, t he volt age st andard is ? terminal = vss terminal volt age. * vd1 = between ?u b1- ?t?c ?u d2 ???u b2- ?u?c ?u d3 ?? vb3- ?v?c ?u b4 ???u dd- ?u ss ?c t e rminal volt age. sany o electric co .,ltd. semiconductor comp any module systems division r e v . 11.oct.2002 1/9
sany o inv e rter power hy br id modul e sip full m o lded package tent a tive ?t?d electri cal characteristics at t c =25 ?? , vd=15v ratin g s p a r a m e t e r s s y mbols c o n d i t i o n s t e s t circuit m i n . t y p . max. unit po w e r output p a rt collector-to-emitter cut-of f c u rrent ?h ce ?u ce= 6 0 0 v f i g . 1 ?] ?] 2 m a upp e r side ?] 2 . 2 3 . 0 v coll ector-to-e m itter saturation volt ag e vce ( sat ) io=5a lo w e r side f i g.2 ?] 2 . 4 3 . 2 v upp e r side ?] 1 . 6 2 . 5 v diod e for w ar d volt ag e ?u f i o =-5 a lo w e r side fig . 3 ?] 1 . 8 2 . 7 v ?? j - c ( t ) i g b t ?] - 7 . 0 ?] junctio n -to-su bstrate therm a l resist ance j - c ( d ) f w d ? - 8 . 0 ? ?? /w control (pre-dr i ver) p a rt ?u d1,2,3=15v ?] 0 . 0 5 1 contro l po w e r suppl y co ns umptio n electric curr ent ?h d ?u d4= 15v f i g.4 ?] 2 1 0 ma input on volt a ge ?u i h o u t p u t o n ?] ?] ?] 0 . 8 v input of f volt age ?u i l o u t p u t o f f ?] 3 . 0 ?] ?] v protection p a rt overcurrent pr otection e l ectri c current ?h s d p w = 1 0 0 ? s f i g.5 1 0 ?] 1 8 a pre-drive p o w e r suppl y l o w volt age protectio n ?t v s d - 1 0 ?] 1 2 v f ault termina l i nput el ectric cu rrent ?h o s d v f aul t = 1 . 0 v - - 2 ?] m a f ault clear ness dela y time f l t c lr each af ter protectio n oper ation end i ng - 6 9 1 2 m s ?? o n 0 . 5 1 . 0 ?] s w itc h i ng time ?? off io= 5a, inducti ve loa d f i g.6 ?] 1 . 0 2 . 0 ? s electric curre nt output sig nal l e vel ?h s o i o = 5 a ?] 0 . 1 5 8 0 . 1 6 7 0 . 1 7 6 v in the case without the instruction, t he volt age st andard is ?| terminal ?? ?u ss terminal volt ag e. notes ?p?d input on vo lt age indicat e s a value t o turn on ou tput st age i g bt . input off volt age indicate s a value to turn of f output st age igbt . at the time of output on, set the in put signal v o lt age 0v to ?u ih (max). at the time of output off , set the in put signal v o lt age ?u il (min) to 5v . ?q?d when the internal prot ection cir c uit operates, there is f a ul t signal on (when the f a ul t terminal is low level, f a ul t signal is on st ate : output form is open drain) but the f a ul t sign al doesn't latch. af ter protection op eration ending, it returns automatically within about 9 ms a nd it becomes an operation beginning co ndition. so, af ter f a ul t signal det ection, set off (high) t o all sany o electric co .,ltd. semiconductor comp any module systems division r e v . 11.oct.2002 2/9
sany o inv e rter power hy br id modul e sip full m o lded package tent a tive input signals at once. b u t, the oper ation of pre- drive power supply low volt age prote c tion (uvlo: it has a hysteresis about 0 . 3v) is as follows. upp e r side ? there is not f a ul t signal output but it does a corr esponding gate signa l off . in cident ally , it r e turns to th e regular o peration wh e n recovering t o the normal volt age but the latch co ntinues amo ng input sig nal on (low). lower side ? it output s f a ul t signal with gate signal off . however , it dif f erent fro m the protection operatio n of upper side, it is automatically reset about 9 ms later and becomes an operation begin n ing condition wh en recovering to the nor mal volt age. (the protection operatio n doesn't lat c h by the in put signal.) ?r?d when asse mbling the h y brid ic on t he heat sink, tightening t o rque range is 0.8n ?e m to 1.0n ?e m. ?s?d the pre-drive low volt age protection is the f eatur e to protect a device when the pre-d r iver supply volt age declines with the operating malfunction. as for th e p r e-driver supply volt age decline in case of operation beginning, a nd so on, we request co nfirmation in the set. sany o electric co .,ltd. semiconductor comp any module systems division r e v . 11.oct.2002 3/9
sany o inv e rter power hy br id modul e sip full m o lded package sany o electric co .,ltd. semiconductor comp any module systems division r e v . 11.oct.2002 4/9 tent a tive 6. circuit bl ock diagram v b 1( 8) u( 9 ) v b 2( 5) v( 6 ) vb 3 ( 2 ) w( 3 ) ?{ ( 11) ?| ( 13) h i n 1 ( 14) h i n 2 ( 15) h i n 3 ( 16) l i n 1 ( 17) l i n 2 ( 18) l i n 3 ( 19) fa u l t ( 2 0 ) is o ?i 2 1 ) v dd( 2 2 ) vs s ( 2 3 ) lo g i c le v e l sh i f t e r lo g i c le v e l sh i f t e r lo g i c le v e l sh i f t e r cb cb cb shu nt r e s i s t o r la t c h o v e r - c u rre n t v dd- u n d e r v o l t a g e u. v . u. v. u. v . la t c h t i m e a b o u t 9 m s ( au t o ma t i c r e s e t )
sany o inv e rter power hy br id modul e sip full m o lded package tent a tive 7. t est circ uit ?q ?r ?t ?u ?w ?x ?q?q ?q?r vd3 ?? 15v vd2 ?? 15v vd1 ?? 15v vd4 ?? 15v ?q ?r ?t ?u ?w ?x ?q?q ?? ?q?r vd3 ?? 15v vd2 ??15v vd1 ?? 15v vd4 ?? 15v ?l ?m fig ?p ?f ?h ce fig ?q ?f ?u ce(sat) ?l ?m ?` ?h ce ?u ce m n u+ 11 9 v+ 11 6 w+ 11 3 u- 9 13 v- 6 13 w- 3 13 ?h o ?u ce(s at) ?u m n m u+ 11 9 14 v+ 11 6 15 w+ 11 3 16 u- 9 13 17 v- 6 13 18 w- 3 13 19 fig ?r ?f ?u f m n u+ 11 9 v+ 11 6 w+ 11 3 u- 9 13 v- 6 13 w- 3 13 ?l ?m ?u f ?u ?h o fig ?s ?f ?h d m n vd1 8 9 vd2 5 6 vd 3 2 3 vd4 22 23 ?` ?h d ?ud ?? ?? ?? sany o electric co .,ltd. semiconductor comp any module systems division r e v . 11.oct.2002 5/9
sany o inv e rter power hy br id modul e sip full m o lded package tent a tive ?q ?r ?t ?u ?w ?x ?q?q ?p?v ?q?r vd 3 ?? 15 v vd2 ?? 1 5 v vd 1 ?? 1 5 v vd 4 ?? 1 5 v in pu t sig na l ?q ?r ?t ?u ?w ?x ?q?q ?p?v ?q?r vd 3 ?? 1 5 v vd 2 ?? 1 5 v vd 1 ?? 1 5 v vd 4 ?? 1 5 v in pu t s i g n a l ?x ?p?r ?ho fig ?t ?f ?h sd f i g ?u ?f s w itc hi ng t ime inp ut si gn al ?ho ?hs d 10 0 ? s ?b?r ?uc c ?ho ?p?p ?x ?p?r i n p u t si gn al ?ho ??on ?? off 10 ?? 90 ?? ?i0 ?`5 ?u ?j sany o electric co .,ltd. semiconductor comp any module systems division r e v . 11.oct.2002 6/9
sany o inv e rter power hy br id modul e sip full m o lded package tent a tive 8. example of the application circuit 2 3 5 6 8 9 1 1 13 14 15 16 17 18 19 20 21 22 23 control logic vdd=15v lin3 lin2 lin1 hin3 hin2 hin1 vdd iso vss fault ?{ ?| vcc cb cb cb db db db rb cs ci STK621-015 cd u vb1 v vb2 w vb3 ?{ ?| 9. recommendation operating conditions v a lue parameters s y m b o l c o n d i t i o n s m i n . t y p . m a x . unit supply volt a ge vcc ?{ - ?| 0 2 8 0 400 v vd1,2,3 vb1 - u,vb2 - v , vb3 - w 12.5 15 17.5 pre-driver supply volt ag e vd4 vdd - vss ?|?p 1 3 . 5 1 5 16.5 v input on vol t age vin(on) 0 ?| 0.3 input off volt age vin(off) hin1,hin2, hin3, lin1,lin2,lin3 t e rminal 3.5 ?| 5 v pwm freque ncy fpwm 1 ?| 2 0 k h z dead t i m e d t upper/lower input signal downtime 2 ?| ?| ? s t i ghtening t o rque mt ?e?l?r?f t y pe screw 0.8 ?| 1.0 n m ?|?p pre-drive power supply (vd4=1 5 ?} 1.5v) must have the cap a city of io=20ma(dc), 0.5a(pe a k). usage precautions 1. by the addition of the diode for the boot strap (db : high spe ed type, withst and volt age equal to or more than 6 00v) and of the cap a cito r (cb : abou t 1 to 47 ? f), a single power supply d r ive is enabled. in this case, it makes a lower side igbt on (in put signal of lower side makes low ) . then it ch arge s sany o electric co .,ltd. semiconductor comp any module systems division r e v . 11.oct.2002 7/9
sany o inv e rter power hy br id modul e sip full m o lded package tent a tive in cb. incident ally , in c a se of st art-up and so o n , when the volt age of cb is low , t he big charging electric curr ent flows an d sometime s becomes t he cause w h ich exert s the bad influ ence of the noise and so on. put limit ation resist ance rb (se v eral ? to abo ut tens of ? ). (when not using boot strap circuit, each upper side pre-drive power supply needs an in dependent p o wer supply . externally set.) also, the up per side po wer supply volt age sometimes declin es by the way of controlling. confir m it. 2. because th e jump volt age which is accomp anied by the vibration in case of swit ching opera t ion occurs by t he influence of the float ing induct a n c e of the wiring of the outer power supply which is connected with of the + terminal and the ?terminal, restrain s and sp ares serge volt age being a s the connection of the snubb er circu i t (c ap acitor / c s / about 0. 1 - 10 f) fo r the volt age absorption with the neighbo rhood as po ssible between + and th e - terminal, and so on , with making a wiring len g th (among the terminals each from ci) short and making a wirin g induct ance small. 3. iso terminal (20pin) is fo r the electric current monitor . be car e ful, because the overcurrent protect i on does not op erate when short-circu i ting in the iso terminal and the vss te rminal. 4. output form of the f a ul t terminal is open dra in (it is operating as f a ul t when b e coming low). when the pull up with th e resist ance , use above 5.6k ? . 5. zener diode with 5v (5 .0-5.4v) is connected with the inside of the signal input t e rminal. when inputting th e volt age which exceeds 5 v , connect resist or to b e tween the side of the p o wer and t h e signal input terminal, for the input current of the signal input terminal be come equal to or less t han 0.5ma. this resistor is e f fective with the noise ab sorption of t he signal ter m inal, too. 6. the overcurrent protection feature o perates only when it is p o ssible to d o a circu i t control normally . for the safe ty , put a fuse, and so on in the vcc line. 7. because th e ic sometimes destroys and burst s when mo tor connection terminal (3pin,6pin,9 p in) becomes open while the motor t u rns, especially , be careful of the connection ( the soldering condition ) o f this termin al. this dat a shows the example of the application circuit, d oes not guarantee a design as th e mas s production set sany o electric co .,ltd. semiconductor comp any module systems division r e v . 11.oct.2002 8/9
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